Portable electronic devices are ubiquitous accoutrements in modern life. Cellular telephones, smartphones, satellite navigation receivers, e-book readers and tablet computers, wearable computers (e.g., glasses, wrist computing), cameras, and music players are just a few examples of the many types of portable electronic devices in widespread use. Portable electronic devices are powered by batteries—either replaceable batteries such as alkaline cells, or rechargeable batteries such as NiCd, NiMH, LiOn, or the like. In either case, the useful life of portable electronic devices is limited by available battery power, which decreases in proportion to the length of use of the device, and the level of power consumption during that use.
Trends in portable electronic device design exacerbate the problem of limited available power. First, device form factors tend to shrink, due to increasing integration of electronics and miniaturization of component parts, such as disk drives. This forces the size of the battery to shrink as well, which generally reduces the available energy storage capacity. Second, electronic devices are increasingly sophisticated, offering new applications, more sophisticated user interfaces, enhancements such as encryption, and the like. The additional software implementing these features requires increased computational power to execute, which translates to larger, or additional, processors and more memory. Finally, successive generations of portable electronic device often add additional features such as various modes of wireless connectivity, which may require the integration of additional chip sets and other electronics. An increase in the demand for power by more processors and circuits, coupled with ever-shrinking battery size and capacity, has made power management a critical area of optimization for portable electronic device designers.
Several approaches to power management are known in the art. One such approach is to identify circuits (or sub-circuits) that are not used for extended periods, and put them into a low-activity state, also referred to as a “sleep” mode, even if other circuits in the device are fully active. As one example, the illuminated display screen of many devices will shut off after a (selectable) duration of no user interactivity. One way to shut down digital circuits is to isolate clocks signals from these circuits. Since storage elements within the digital circuits only change state in response to clock signal edges or levels, power-consuming electrical activity within the circuits effectively ceases.
A more sophisticated approach to the “sleep” technique is to match the frequency of a clock signal to the level of activity of a digital circuit. For example, a processor engaged in heavy computation may be clocked at a high frequency, to extract maximum performance. However, when the processor is performing merely background tasks, the frequency of its clock signal may be reduced without a user-noticeable degradation of performance, which concomitantly reduces the power consumed.
Another approach to power management is to vary the power supplied to various circuits (or sub-circuits) according to the instantaneous load of the circuit. In this manner, circuits that are engaged in computation or other activity are provided sufficient power to operate, and circuits experiencing a lighter load are provided with a lower level of current.
All of these power management techniques are problematic when applied to a wireless modem 58, as depicted in FIG. 22, which may include a digital broadband integrated circuit (IC) 60, radio frequency IC 62, and power amplifier 64. When a user is actively using the data connection and expecting high download speed and short latency, the modem 58 is configured with highest performance settings, such as high speed clocks, full power, and all circuits enabled. When the data connection requirements are relaxed, there is an opportunity to save power by lowering the wireless modem 58 performance, such as by lowering clock frequencies, gating clocks to some circuits, lowering supply voltages, and shutting down circuits that are not used. Such wireless modem 58 throttling is limited by the fact that the user may resume data connection usage at any time, and the wireless modem 58 must return from a power-saving mode to full performance, without user-perceptible delay. This means that the wireless modem 58 has a few tens of milliseconds to resume from a power-saving mode to a high performance mode.
When the wireless modem enters a limited performance or power-saving mode, voltage regulators may be configured to a mode where output current capability is limited. Another power-saving measure is to limit clock signal distribution to switching mode analog blocks (e.g., Switched Mode Power Supply) by digital control such as clock gating, or even disabling the clock generation circuit completely. Disabling the clock generation circuit achieves the best power savings, but it can be done only when none of the wireless modem circuits require a clock signal. Another constraint is that the clock generation circuit must have a start-up time fast enough to satisfy the full power transition time requirements of all blocks receiving the clock signal(s).
New generations of wireless modem design simultaneously require higher frequency and reduced power consumption. For example, a 6.5 MHz control bus is targeted, in future designs, to operate at 26 MHz. One approach to reaching these challenging design goals is to enter restricted-clock, or “sleep” mode more often. However, this requires a very fast start-up time from the dormant state, such as 1.5 u-sec, compared to current designs of 10 u-sec.
A large challenge to designing a clock generation circuit with a fast start-up time, but which consumes little power during operation, is that RC factors are large and bias currents are small. As intermediate nodes begin to charge from ground (or supply voltage), they not only charge slowly but also it takes time for transient perturbations in the node voltages to settle. Settling of the node voltages at the proper operating values is essential to achieve an accurate clock signal.
Known approaches to decreasing the clock generation circuit start-up time include boosting bias currents, disconnecting capacitors, and transferring target voltages directly to intermediate and output nodes. All of these approaches suffer from the deficiency that once intermediate circuit nodes are charged, it still takes time to settle the node voltage sufficiently to achieve frequency stability. Accordingly, the known approaches are insufficient to reduce clock generation circuit start-up time by the necessary amount.
Korean Patent Publication No. KR-20050074755 by K. Han, titled “Low power relaxation oscillator circuit,” describes a boost circuit that injects current into both nodes n1 and n2 of the capacitor C of a relaxation oscillator.
The paper by T. Tokairin, et al., titled, “A 280 nW, 100 kHz, 1-Cycle Start-up Time, On-chip CMOS Relaxation Oscillator Employing a Feedforward Period Control Scheme,” published in the 2012 Symposium on VLSI Circuits Digest of Technical Papers, p. 16, describes a scheme to shift the oscillator switching delay to prior to a comparator reaching a reference voltage as the capacitor charges. This is accomplished by doubling the charging current at the beginning of every half cycle of oscillation, which the authors refer to as “boost charging.”
U.S. Pat. No. 7,005,933 to J. Shutt describes a dual mode relaxation oscillator that generates clock signals in both normal and low-power mode, with the clock in low-power mode being less accurate.
U.S. Pat. No. 4,250,464 to O. Schade describes a multi-mode relaxation oscillator which generates a lower frequency clock signal in low-power mode than in normal operating mode.
The Application note AN9334.2 published by Intersil Corporation, titled “Improving Start-up Time at 32 KHz for the HA7210 Low Power Crystal Oscillator,” December 2000, describes a crystal oscillator having an enable pin operative to turn off an output buffer in stand-by mode to save power. The internal oscillator continues to run in stand-by mode. Power savings are limited to 50%.
None of these prior art solutions can achieve a high frequency clock generation circuit having a low-power mode with approximately 90% power consumption reduction, yet with very short start-up time to return to full operating mode of approximately 1.5 u-sec.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.